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 HD74LVCZ16244A
16-bit Buffers / Line Drivers with 3-state Outputs
REJ03D0374-0200 (Previous ADE-205-232 (Z)) Rev.2.00 Aug. 19, 2004
Description
The HD74LVCZ16244A has sixteen line drivers with three state outputs in a 48 pin package. This device is a non inverting buffer and has four active low enables (1G to 4G). Each enable independently controls four buffers. When VCC is between 0 and 1.5 V, the device is in the high impedance state during power up or power down. Low voltage and high-speed operation is suitable at battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation.
Features
* * * * * * * * * VCC = 2.7 to 5.5 V All inputs VIH (Max) = 5.5 V (@VCC = 0 to 5.5 V) All outputs VO (Max) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25C) High impedance state during power up and power down Power off disables outputs, permitting live insertion High output current 24 mA (@VCC = 3.0 to 5.5 V) Ordering Information
Package Type TSSOP-48 pin Package Code TTP-48DBV Package Abbreviation T Taping Abbreviation (Quantity) EL (1,000 pcs/reel)
Part Name HD74LVCZ16244ATEL
Function Table
Inputs G H L L H: High level L: Low level X: Immaterial Z: High impedance A X H L Output Y Z H L
Rev.2.00 Aug. 19, 2004 page 1 of 7
HD74LVCZ16244A
Pin Arrangement
1G 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7 2Y1 8 2Y2 9 GND 10 2Y3 11 2Y4 12 3Y1 13 3Y2 14 GND 15 3Y3 16 3Y4 17 VCC 18 4Y1 19 4Y2 20 GND 21 4Y3 22 4Y4 23 4G 24
48 2G 47 1A1 46 1A2 45 GND 44 1A3 43 1A4 42 VCC 41 2A1 40 2A2 39 GND 38 2A3 37 2A4 36 3A1 35 3A2 34 GND 33 3A3 32 3A4 31 VCC 30 4A1 29 4A2 28 GND 27 4A3 26 4A4 25 3G
(Top view)
Absolute Maximum Ratings
Item Supply voltage Input voltage Output voltage Input diode current Output diode current Output current VCC, GND current Storage temperature Symbol VCC VI VO IIK IOK IO ICC or IGND Tstg Ratings -0.5 to 7.0 -0.5 to 7.0 -0.5 to 7.0 -0.5 to VCC+0.5 -50 -50 50 100 -65 to 150 Unit V V V mA mA mA mA C Conditions
Output "Z" or VCC : OFF Output "H" or "L" VI < 0 VO < 0
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Rev.2.00 Aug. 19, 2004 page 2 of 7
HD74LVCZ16244A
Recommended Operating Conditions
Item Supply voltage Input voltage Output voltage Output current Symbol VCC VI VO IOH IOL Input rise / fall time Operating temperature Note: 1. Duty cycle 50% tr, tf Ta Ratings 2.7 to 5.5 0 to 5.5 0 to 5.5 0 to VCC -12 -24 *1 12 24 *1 0 to 6 -40 to +85 Unit V V V mA mA ns / V C Conditions At operation Output "Z" or VCC : OFF Output "H" or "L" VCC = 2.7 V VCC = 3.0 to 5.5 V VCC = 2.7 V VCC = 3.0 to 5.5 V
Logic Diagram
1G 1A1
1
2G
2
48
47
1Y1
2A1
41
8
2Y1
1A2
46
3
1Y2
2A2
40
9
2Y2
1A3
44
5
1Y3
2A3
38
11
2Y3
1A4
43
6
1Y4
2A4
37
12
2Y4
3G 3A1
25
4G
13
24
36
3Y1
4A1
30
19
4Y1
3A2
35
14
3Y2
4A2
29
20
4Y2
3A3
33
16
3Y3
4A3
27
22
4Y3
3A4
32
17
3Y4
4A4
26
23
4Y4
Rev.2.00 Aug. 19, 2004 page 3 of 7
HD74LVCZ16244A
Electrical Characteristics
(Ta = -40 to 85C) Item Input voltage Symbol VIH VIL Output voltage VOH VCC (V) 2.7 to 3.6 4.5 to 5.5 2.7 to 3.6 4.5 to 5.5 2.7 to 5.5 2.7 3.0 3.0 4.5 2.7 to 5.5 2.7 3.0 4.5 0 to 5.5 2.7 to 5.5 0 to 1.5 1.5 to 0 0 2.7 to 3.6 2.7 to 5.5 2.7 to 3.6 3.3 3.3 Min 2.0 VCCx0.7 -- -- VCC-0.2 2.2 2.4 2.2 3.8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4.1 8.1 Max -- -- 0.8 VCCx0.3 -- -- -- -- -- 0.2 0.4 0.55 0.55 5 5 5 5 5 225 350 500 -- -- Unit V V V IOH = -100 A IOH = -12 mA IOH = -24 mA V IOL = 100 A IOL = 12 mA IOL = 24 mA VIN = 0 to 5.5 V VOUT = 0 to 5.5 V VOUT = 0.5 to 5.5 V, Output enable = don't care A A A pF pF VIN or VO = 5.5 V VIN = 3.6 to 5.5 V *1, IO = 0 VIN = VCC or GND VIN = one input at (VCC-0.6) V, other inputs at VCC or GND VIN = VCC or GND VOUT = VCC or GND Test Conditions
VOL
Input current Off state output current Output leak current Quiescent supply current
IIN IOZ IOZPU IOZPD IOFF ICC ICC
A A
Input capacitance Output capacitance Note:
CIN CO
1. This applies in the disabled state only.
Switching Characteristics
FROM (Input) A (Ta = -40 to 85C) TO (Output) Y
Item Propagation delay time
Symbol tPLH tPHL tZH tZL tHZ tLZ
VCC (V) 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5
Min -- 1.1 -- -- 1.0 -- -- 1.8 -- -- -- --
Typ -- -- -- -- -- -- -- -- -- -- -- --
Max 4.7 4.1 3.8 5.8 4.6 4.4 6.2 5.8 4.6 -- 1.0 1.0
Unit ns
Output enable time
ns
G
Y
Output disable time
ns
G
Y
Between output pin skew *1 tOSLH tOSHL Note:
ns
1. This parameter is characterized but not tested. tOSLH = |tPLHm-tPLHn|, tOSHL = |tPHLm-tPHLn|
Rev.2.00 Aug. 19, 2004 page 4 of 7
HD74LVCZ16244A
Test Circuit
VCC VCC Output 1G to 4G Input Pulse generator Zout = 50 500 1Y1 to 4Y4 1A1 to 4A4 C L= 50 pF 450
50 Scope
See Function Table
S1
*1
OPEN See under table GND
Symbol t PLH / t PHL t ZH/ t HZ t ZL / t LZ Note: 1. C L includes probe and jig capacitance.
S1
Vcc=2.7V, 3.30.3V Vcc=5.00.5V
OPEN GND 6V
OPEN GND 2xVCC
Rev.2.00 Aug. 19, 2004 page 5 of 7
HD74LVCZ16244A
* Waveforms - 1
tr 90 % Vref 10 % t PLH 90 % Vref
tf VIH 10 % t PHL GND
Input A
VOH Output Y Vref Vref VOL
* Waveforms - 2
tf 90 % Vref 10 % t ZL 10 % t LZ tr 90 % Vref GND VOH1 Waveform - A Vref t ZH t HZ VOH - 0.3 V VOL + 0.3 V VOL VOH VOL1 TEST VIH Vref VOH1 VOL1
Vcc=2.7V, 3.30.3V Vcc=5.00.5V
VIH
Input G
Waveform - B
Vref
2.7 V 1.5 V 3V GND
VCC 50%VCC VCC GND
Notes: 1. Input waveform : PRR = 10 MHz, duty cycle 50%, t r = 2.5 ns, t f = 2.5 ns 2. Waveform - A shows input conditions such that the output is "L" level when enabled by the output control. 3. Waveform - B shows input conditions such that the output is "H" level when enabled by the output control.
Rev.2.00 Aug. 19, 2004 page 6 of 7
HD74LVCZ16244A
Power up / down Characteristics
4.0
Ta = 25C Output enable = "L"
3.0
VOUT (V)
2.0 Disable area Enable area
1.0
0 0 1.0 2.0 VCC (V) 3.0 4.0
Package Dimensions
As of January, 2002
12.5 12.7 Max 48 25
Unit: mm
1 *0.19 0.05
0.50
24
0.08 M 8.10 0.20 0 - 8
6.10
1.0
0.65 Max
*0.15 0.05
0.10
0.10 0.05
1.20 Max
0.50 0.1
*Pd plating
Package Code JEDEC JEITA Mass (reference value)
TTP-48DBV -- -- 0.20 g
Rev.2.00 Aug. 19, 2004 page 7 of 7
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
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http://www.renesas.com
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